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Saturday, August 14, 2010

CS302- Digital Logic Design (Session - 4) (Part 1 of 2)

FINALTERM EXAMINATION

Spring 2010

CS302- Digital Logic Design (Session - 4)

Time: 90 min

Marks: 58

Question No: 1 ( Marks: 1 ) - Please choose one

The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format for binary numbers.

8-bit

16-bit

► 32-bit

64-bit

Question No: 2 ( Marks: 1 ) - Please choose one

The decimal “17” in BCD will be represented as _________

► 11101

► 11011

► 10111

► 11110

Question No: 3 ( Marks: 1 ) - Please choose one

The basic building block for a logical circuit is _______

► A Flip-Flop

► A Logical Gate

► An Adder

► None of given options

Question No: 4 ( Marks: 1 ) - Please choose one

The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.

► Undefined

► One

► Zero

► No Output as input is invalid.

Question No: 5 ( Marks: 1 ) - Please choose one

________ is invalid number of cells in a single group formed by the adjacent cells in K-map

2

8

12

16

Question No: 6 ( Marks: 1 ) - Please choose one

The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.

AND

OR

NOT

XOR

Question No: 7 ( Marks: 1 ) - Please choose one

___________ is one of the examples of synchronous inputs.

► J-K input

► EN input

► Preset input (PRE)

► Clear Input (CLR)

Question No: 8 ( Marks: 1 ) - Please choose one

___________ is one of the examples of asynchronous inputs.

► J-K input

► S-R input

► D input

► Clear Input (CLR)

Question No: 9 ( Marks: 1 ) - Please choose one

The _____________ input overrides the ________ input

Asynchronous, synchronous

Synchronous, asynchronous

Preset input (PRE), Clear input (CLR)

Clear input (CLR), Preset input (PRE)

Question No: 10 ( Marks: 1 ) - Please choose one

__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.

Race condition

Clock Skew

Ripple Effect

None of given options

Question No: 11 ( Marks: 1 ) - Please choose one

Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________

► 0000

► 1101

► 1011

► 1111

Question No: 12 ( Marks: 1 ) - Please choose one

In a state diagram, the transition from a current state to the next state is determined by

Current state and the inputs

Current state and outputs

Previous state and inputs

Previous state and outputs

Question No: 13 ( Marks: 1 ) - Please choose one

________ is used to minimize the possible no. of states of a circuit.

State assignment

State reduction

Next state table

State diagram

Question No: 14 ( Marks: 1 ) - Please choose one

________ is used to simplify the circuit that determines the next state.

State diagram

Next state table

State reduction

State assignment

Question No: 15 ( Marks: 1 ) - Please choose one

The best state assignment tends to ___________.

Maximizes the number of state variables that don’t change in a group of related states

Minimizes the number of state variables that don’t change in a group of related states

Minimize the equivalent states

None of given options

Question No: 16 ( Marks: 1 ) - Please choose one

The output of this circuit is always ________.

http://vuzs.net/images/stories/Q16.jpg

► 1

► 0

► A

Question No: 17 ( Marks: 1 ) - Please choose one

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

1

2

4

8

Question No: 18 ( Marks: 1 ) - Please choose one

5-bit Johnson counter sequences through ____ states

7

10

32

25

Question No: 19 ( Marks: 1 ) - Please choose one

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

1100

► 0011

► 0000

► 1111

Question No: 20 ( Marks: 1 ) - Please choose one

The address from which the data is read, is provided by _______

Depends on circuitry

None of given options

RAM

Microprocessor

Question No: 21 ( Marks: 1 ) - Please choose one

FIFO is an acronym for __________

First In, First Out

Fly in, Fly Out

Fast in, Fast Out

None of given options

Question No: 22 ( Marks: 1 ) - Please choose one

LUT is acronym for _________

Look Up Table

Local User Terminal

Least Upper Time Period

None of given options

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